Control units are known from the related art which have a main arithmetic unit and a separate model computation unit for computing data-based function models. For example, the publication DE 10 2010 028 266 A1 shows a control unit having an additional logic circuit as the model computation unit which is designed for purely hardware-based computation of multiplications, additions, and exponential functions in one or more loop computations. This makes it possible to support Bayesian regression processes, which are needed in particular for the computation of Gaussian process models, in a hardware unit.
The model computation unit is designed overall to carry out mathematical processes for computing the data-based function model based on parameters and node or training data. The model computation unit is, in particular, designed for efficient hardware-based computation of exponential functions in two computational loops, so that it is possible to compute Gaussian process models at a higher computation rate than may take place in the software-operated main arithmetic unit. In order to accelerate the computation in the logic unit, multiplication and addition processes may be combined in a joint multiplier-accumulator (MAC) or FMA unit which makes a hardware implementation available for an addition and a multiplication operation in a particularly efficient manner.
For example, U.S. Pat. No. 7,080,111 describes such an FMA unit for an input-side and an output-side resolution of 32 bits, and U.S. Pat. No. 7,346,642 also shows such an FMA unit which, however, is more accurate.